1. Technical Field
The present invention relates generally to integrated circuit design, and more particularly, to a method, system and program product for statistically modeling a circuit relative to processing, and especially random dopant variation.
2. Related Art
All integrated circuit (IC) manufacturing lines are subject to random variation in process conditions that cause random variation in the chips produced. Chips of the same design will differ in random ways, and within a single chip, transistors of the same design will differ in random ways. In order to ensure that a design will function correctly when manufactured, the designer needs to simulate the range of expected variations during the design process. The simplest and most common approach to this problem is to simulate a small set of extreme “corner” model parameters. In this approach, several models that represent extremes of process variations are tested. Typically, five corners are defined in which particular settings for NFETs and PFETs speeds are made: TT=typical NFET and PFET, FF=fast NFET and fast PFET, SS=slow NFET and slow PFET, FS=fast NFET and slow PFET and SF=slow NFET and fast PFET. The fast and slow settings are typically generated by using a value that is mean plus or minus some multiple of standard deviation. Unfortunately, this approach does not provide the ability to customize the corners to individual circuit sensitivities. For example, some circuits are more sensitive to process variations that affect threshold voltage (Vt) than to those that affect channel length. For example, in analog circuits where different transistors perform different functions, a larger set of corners is typically required to ensure all circuit requirements are met. For circuits that depend on matching between devices, it may be necessary to skew different devices in different ways within the same simulation. For some complicated circuits it may not be possible to anticipate which of the infinite possible combinations of parameter skews will be limiting cases for all of the circuit characteristics of interest.
One approach to address the above-identified problem has been to implement a Monte Carlo model in which random test cases are generated. In this model, some model parameters are specified as a distribution, typically a Guassian distribution with a specified mean, and standard deviation. The best conventional Monte Carlo models provide correlation between parameters by specifying multiple parameters using a single distribution. For example, per edge delta channel length (lint) for several different FET types may be specified by a single distribution. In this case, each parameter can have its own mean and standard deviation: Pi=Pi, nom+Pi, tol*x, where x is a normally distributed variable with a mean of zero and standard deviation of 1. Unfortunately, this approach requires a careful description of the process variations and the correlations between them so that a full range of variations is explored without testing cases that are impossible, e.g., longest possible PFETs and shortest possible NFETs, which are incompatible due to their required lithography processes. This approach also does not allow representation of situations where only partial correlations between model parameters exist. Providing the multitude of run cycles necessary to consider all of the possible partial correlations makes run times excessive. Accordingly, conventional Monte Carlo approaches cannot be used for most circuit design work.
To provide some further functionality, some conventional Monte Carlo models use a “corner” model of some type with fixed corners, or a model with a set of user controllable model parameters so that the model parameters can be moved about in the process variation space. The best corner models typically include several user settable model parameters and each Monte Carlo distribution is assigned to exactly one of the user controllable corner parameters. However, these models still do not adequately represent situations where only partial correlations between model parameters exist.
Another challenge is modeling parameters that cannot be directly measured. One particular model parameter that cannot be directly measured but is increasingly becoming problematic relative to process scaling for advanced complementary metal-oxide semiconductor (CMOS) technologies is local fluctuation (i.e., mismatch variation) of the threshold voltage (Vt) and channel current (IDS). Local fluctuations increase as the device becomes smaller. Some of the main causes of local fluctuation are the randomness of doping variation, local variation of the geometries such as a gate oxide thickness, and the effective channel length and width. These physical causes make the fluctuation of threshold voltage (Vt) and channel current (IDS) larger in smaller devices. Because the physical causes are correlated to the statistical nature of ion implantation, it is not possible to eliminate these variations. As a result, circuit designers are faced with less design margin with continued miniaturization because the threshold voltages (Vt) are not scalable as much as others, which increases the ratio of the threshold voltage (Vt) variation to supply voltage (VDD). Due to the nature of the fluctuation and continued scaling, more accurate modeling of this random local fluctuation is increasingly critical in predicting circuit performance.
Conventionally, the spice-based compact modeling for the random fluctuation of threshold voltage (Vt) and channel current (IDS) is focused on the dependency of the variation on the device's geometry. But, based on the aforementioned physical causes, there exists a strong correlation between the fluctuations of threshold voltage (Vt) and channel current (IDS) in different bias conditions, or between threshold voltages (Vt) and channel current (IDS). Currently, no methodology exists to introduce the correlation between the fluctuations of threshold voltage (Vt) and channel current (IDS) into the model in addition to the geometry dependent variation. Consequently, the assumption that variations are uncorrelated results in pessimistic predictions in the variation. In addition, conventional spice-based compact modeling does not provide mathematical relationships to the physical process variations.
In view of the foregoing, a need exists in the art for an improved modeling approach.